1. Field of the Invention
The present invention relates to a sensor signal processor for use in measurements.
2. Description of the Related Art
Optical and magnetic encoders are now in widespread use as position detection sensors. To increase encoder resolution, conventional systems have electrically multiplied the analog sine waves that are output from the encoder, without smaller divisions of scale in the encoder.
FIG. 11 illustrates the relationship between an example of a contrast pattern of detected light and the pattern of a photodiode array in a photo receiver used in an optical encoder functioning as a position detection sensor. Photodiode arrays S1 to S4 are arranged out of phase by 0°, 90°, 180°, and 270°, respectively, with respect to the contrast pattern.
FIG. 12 is a circuit diagram of a signal processor for processing signals supplied from the photodiode arrays S1 to S4 in FIG. 11. Referring to FIG. 12, current supplied from each photodiode array S1 to S4 is respectively supplied to each current-voltage converter 300a to 300d. The signals that have been subjected to the current-voltage conversion are out of phase by 0°, 90°, 180°, and 270°, respectively, with respect to the contrast pattern. The signals from the photodiode arrays S1 and S3 are differentially amplified by a differential amplifier 301a and the signals from the photodiode arrays S2 and S4 are differentially amplified by a differential amplifier 301b to provide A-phase and B-phase analog-sine-wave voltage signals A and B that are out of phase by 0° and 90°, respectively, with respect to the contrast pattern.
FIG. 13 illustrates an example of a known resistance dividing circuit, disclosed in Swiss Patent No. 407569, capable of dividing the pitch of a primary signal into 16 sub-divisions by using two-phase analog signals. Signals Asinθ and Acosθ are supplied to buffer amplifiers 20A and 20B. The amplified signals are applied to nodes of resistor arrays R1–R4, along with a signal −Asinθ given by inverting an output from the buffer amplifier 20A by using an inverting amplifier 22. A total of eight comparators 24A to 24H are provided corresponding to the nodes of the resistor array. A reference voltage Vr for comparison is supplied from a reference-voltage adjuster 26 to each of the comparators 24A to 24H. The outputs from the comparators 24A to 24H are synthesized by exclusive OR gates 28A to 28F. The synthesized signals are output from a direction discriminator 30 to which an oscillator 32 is connected.
In this resistance dividing circuit, the ratio of the values of resistors R1 to R4 of the resistor array is set to 1:0.707:0.707:1. Since 180° are divided into eight, 360° are divided into 16.
FIG. 14 is a block diagram of an example of a multiplier circuit (optical encoder). The optical encoder has a sensor unit 41 and a signal processor 42. The sensor unit 41 includes a light emitter 51, scales 54 and 55, and a photo receiver 52. The signal supplied from the photo receiver 52 is amplified by an amplifier 64 and is subjected to arithmetic processing to provide analog signals Asinθ and Acosθ.
The analog signals Asinθ and Acosθ are supplied to first and second analog-to-digital converters 61 and 62 to be converted into digital data. The output signals DA and DB converted into digital data are supplied to a read-only memory (ROM) 63. The signals from the ROM 63 are supplied to a synthesizer 66 and a synthesizer and PA/PB converter 67. Analog amplitude levels (DA)2 and (DB)2 corresponding to the output signals DA and DB are output from the synthesizer 66. Positional information tan−1 (DA/DB) is output from the synthesizer and PA/PB converter 67. A clock generator 65 determines the timing of data sampling. The data is updated in accordance with the timing of a clock pulse.
When the resistance division is performed in the multiplier circuit in FIG. 14, increasing the number of multipliers in order to increase the resolution enlarges the circuit, thus raising the cost. The system for converting the values given by analog-to-digital conversion into positional information as a table must have a sufficient memory corresponding to the table. Accordingly, it is necessary to increase the memory space as the resolution is increased, thus also enlarging the circuit.
Further, in the multiplier circuit in FIG. 14, the sensor unit 41 outputs only the analog signals that are sampled after amplification by using a clock pulse. However, at higher moving speed at which the output from the encoder has higher frequencies, the capacity of the analog-to-digital converters 61 and 62 is insufficient, so that the number of analog waves of the signal can be incorrectly counted.